The present invention relates to the electrical, electronic, and computer arts, and, more particularly, to methods for forming fins in integrated circuits comprising FinFETs.
Multi-gate field-effect transistors (FETs) are of considerable interest because of their superior electrostatic integrity, as well as their promise of lower supply voltages, reduced threshold voltages, and extended scalability. FinFETs are one form of such multi-gate device. In a FinFET, a narrow channel feature (i.e., fin) is raised above the substrate and passes under a gate, which effectively wraps around the fin. The gate is thereby capacitively coupled to the top as well as the sides of the fin. So structured, very little leakage current passes through channel portions of the fin when the device is in the off state. This allows the use of lower threshold voltages and higher switching speeds.
Fins comprising III-V semiconductor material (i.e., III-V fins) can be formed on (111) silicon sidewalls by introducing a wetting layer prior to growing the III-V fins, so that the III-V fins have a growth-front which is single crystalline (111) faceted. After the silicon mandrels are pulled to release these III-V fins, it is often found that the side which was the interface between the silicon sidewalls and the III-V semiconductor (i.e., the Si-IIIV interface) has a significantly rougher surface than the opposite side (i.e., the growth-front). The poor surface roughness of III-V fins can potentially limit electron transport properties, such as mobility and/or injection velocity, thus producing undesirable effects.